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Reliability challenges for barrier/liner system in high aspect ratio through silicon vias

Yunlong Li; Stefaan Van Huylenbroeck; Els Van Besien; Xiaoping Shi; Chen Wu; Michele Stucchi; Gerald Beyer; Eric Beyne; Ingrid De Wolf; Kristof Croes

本站引用的位置4 处,涉及 2 个知识点

  1. Abstract、Introduction、Experiments;电压应力与 I–V 测试;Microelectronics Reliability 54 (2014), pp.1949–1952;核验的是出版社网页对应段落,PDF页未取得

  2. Impact of Si dry etch on liner integrity;Conclusions;Microelectronics Reliability 54 (2014), pp.1949–1952;核验的是出版社网页对应段落,PDF页未取得

  3. Introduction;Conclusions;高深宽比与 barrier/liner 相互影响;Microelectronics Reliability 54 (2014), pp.1949–1952;核验的是出版社网页对应段落,PDF页未取得

  4. Introduction;Experiments;高深宽比结构衬层可靠性;Microelectronics Reliability 54 (2014), pp.1949–1952;核验的是出版社网页对应段落,PDF页未取得